I wonder whether it's the send timing that's the problem. The original OSCCAL for 16MHz was 0xA2, and 0x47 was the optimal 12MHz value. Assuming roughly linear steps, that's about 0.044MHz/step (the way OSCCAL overlaps around 0x80 means that the step is larger than this). Two steps break it, which is about 0.9% variation
I guess that would be a reasonable assumption. There is not too much that can be done to fix send, other than having a "pll" in between. Maybe you could probe by changing osccal between received and send?